Semiconductor Engineering

Supporting Multiple Time Domains In SoC Production Test

Complex system-on-chip (SoC) devices make every stage of the development flow harder, and the challenges continue even after the silicon is fabricated. Automatic test equipment (ATE) screening for ...
EDN

Determining the best test patternsfor production test

Because I work for a provider of test tools that enable andproduce production test patterns, I am often asked what the best patterns areto use for production test. The answer depends on the device ...
EDN

Spectral content of NRZ test patterns

Many digital-communications systems use non-return-to-zero (NRZ) signaling, and system designers have created many NRZ test patterns to test and verify their products. These patterns usually either ...
Electronic Design

Using Timing Constraints For Generating At-Speed Test Patterns

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...
Semiconductor Engineering

Power-Aware Test: Addressing Power Challenges In DFT And Test

Integrated circuit (IC) sizes continue to grow as they meet the compute requirements of cutting-edge applications such as artificial intelligence (AI), autonomous driving, and data centers. As design ...
Electronic Design

What’s The Difference Between ATPG And Logic BIST?

Two test strategies are used to test virtually all IC logic: automatic test pattern generation (ATPG) with test pattern compression and logic built-in self-test (BIST). This article will describe how ...